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atombios_tables.c

#include "atom.h"
#include <fcntl.h>

extern unsigned char * volatile fb_mem, *volatile ctrl_mem;
static struct card_info my_card_info;

struct radeon_pll {
      uint16_t reference_freq;
      uint16_t reference_div;
      uint32_t pll_in_min;
      uint32_t pll_in_max;
      uint32_t pll_out_min;
      uint32_t pll_out_max;
      uint16_t xclk;

      uint32_t min_ref_div;
      uint32_t max_ref_div;
      uint32_t min_post_div;
      uint32_t max_post_div;
      uint32_t min_feedback_div;
      uint32_t max_feedback_div;
      uint32_t best_vco;
};

char *object_names[] = { "NONE",
                   "INTERNAL LVDS",
                   "INTERNAL TMDS1",
                   "INTERNAL TMDS2",
                   "INTERNAL DAC1",
                   "INTERNAL DAC2",
                   "INTERNAL SDVOA",
                   "INTERNAL SDVOB",
                   "SI170B",
                   "CH7303",
                   "CH7301",
                   "INTERNAL DVO1",
                   "EXTERNAL SDVOA",
                   "EXTERNAL SDVOB",
                   "TI TFP513",
                   "INTERNAL LVTM1",
                   "VT1623",
                   "HDMI SI1930",
                   "HDMI INTERNAL",
                   "INTERNAL KLDSCP TMDS1",
                   "INTERNAL KLDSCP DVO1",
                   "INTERNAL KLDSCP DAC1",
                   "INTERNAL KLDSCP DAC2",
                   "SI178",
                   "MVPU FPGA",
                   "INTERNAL DDI",
                   "VT1625",
                   "HDMI SI1932",
                   "DP AN9801",
                   "DP DP501",
                   "INTERNAL UNIPHY",
                   "INTERNAL KLDSCP LVTMA",
                   "INTERNAL UNIPHY1",
                   "INTERNAL UNIPHY2"
};
                   
char *connector_names[] = { "NONE",
                      "SL DVI-I",
                      "DL DVI-I",
                      "SL DVI-D",
                      "DL DVI-D",
                      "VGA",
                      "COMPOSITE",
                      "SVIDEO",
                      "YPbPr",
                      "D_CONNECTOR",
                      "9PIN_DIN",
                      "SCART",
                      "HDMI A",
                      "HDMI B",
                      "LVDS",
                      "7PIN_DIN",
                      "PCIE CONNECTOR",
                      "CROSSFIRE",
                      "HARDCODE_DVI",
                      "DISPLAYPORT",
};


union firmware_info {
      ATOM_FIRMWARE_INFO info;
      ATOM_FIRMWARE_INFO_V1_2 info_12;
      ATOM_FIRMWARE_INFO_V1_3 info_13;
      ATOM_FIRMWARE_INFO_V1_4 info_14;
};

static struct radeon_pll p1pll_s, p2pll_s, spll_s, mpll_s;

int radeon_atom_get_clock_info(struct atom_context *ctx)
{

      int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
      union firmware_info *firmware_info;
      uint8_t frev, crev;
      struct radeon_pll *p1pll = &p1pll_s;
      struct radeon_pll *p2pll = &p2pll_s;
      struct radeon_pll *spll = &spll_s;
      struct radeon_pll *mpll = &mpll_s;
      uint16_t data_offset;

      atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset);

      firmware_info = (union firmware_info *)(ctx->bios + data_offset);

      if (firmware_info) {
            /* pixel clocks */
            p1pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
            p1pll->reference_div = 0;

            p1pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
            p1pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);

            if (p1pll->pll_out_min == 0) {
                  p1pll->pll_out_min = 64800;
            }

            p1pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
            p1pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);

            *p2pll = *p1pll;

            /* system clock */
            spll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
            spll->reference_div = 0;

            spll->pll_out_min = le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
            spll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);

            /* ??? */
            if (spll->pll_out_min == 0) {
#if 0
                  if (radeon_is_avivo(dev_priv))
                        spll->pll_out_min = 64800;
                  else
                        spll->pll_out_min = 20000;
#endif
            }

            spll->pll_in_min = le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
            spll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);


            /* memory clock */
            mpll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
            mpll->reference_div = 0;

            mpll->pll_out_min = le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
            mpll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);

            /* ??? */
            if (mpll->pll_out_min == 0) {
                  if (0) //radeon_is_avivo(dev_priv))
                        mpll->pll_out_min = 64800;
                  else
                        mpll->pll_out_min = 20000;
            }

            mpll->pll_in_min = le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
            mpll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);

      //    mode_info->sclk = le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
      //    mode_info->mclk = le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);

            return true;
      }
      return false;
}

char *object_type_names[] = { "NONE",
                        "GPU",
                        "ENCODER",
                        "CONNECTOR",
                        "ROUTER",
};

char *router_object_names[] = { "NONE",
                        "I2C_EXTENDER_CNTL",
};

void radeon_lookup_gpio(struct atom_context *ctx, uint8_t id)
{
      ATOM_GPIO_I2C_ASSIGMENT gpio;
      int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
      struct _ATOM_GPIO_I2C_INFO *i2c_info;
      uint16_t data_offset;

      atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);

      i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);

      gpio = i2c_info->asGPIO_Info[id];

      printf("    GPIO %d: %04x\n", id, gpio.usClkMaskRegisterIndex *4);
}

static void radeon_print_object(uint16_t obj)
{
    uint8_t obj_id, num, obj_type;

    obj_id = (obj & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
    num = (obj & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
    obj_type = (obj & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;

    if (obj_type == GRAPH_OBJECT_TYPE_CONNECTOR)
      printf("%s, %d, %s (0x%04x)\n",
             object_type_names[obj_type], num, connector_names[obj_id], obj);
    else if (obj_type == GRAPH_OBJECT_TYPE_ENCODER)
      printf("%s, %d, %s (0x%04x)\n",
             object_type_names[obj_type], num, object_names[obj_id], obj);
    else if (obj_type == GRAPH_OBJECT_TYPE_ROUTER)
      printf("%s, %d, %s (0x%04x)\n",
             object_type_names[obj_type], num, router_object_names[obj_id], obj);
    else
      printf("%s, %d, 0x%02x (0x%04x)\n",
             object_type_names[obj_type], num, obj_id, obj);

}

static void radeon_print_supported_devices(uint16_t sd)
{
    if (sd & ATOM_DEVICE_CRT1_SUPPORT)
      printf("CRT1 ");
    if (sd & ATOM_DEVICE_LCD1_SUPPORT)
      printf("LCD1 ");
    if (sd & ATOM_DEVICE_TV1_SUPPORT)
      printf("TV1 ");
    if (sd & ATOM_DEVICE_DFP1_SUPPORT)
      printf("DFP1 ");
    if (sd & ATOM_DEVICE_CRT2_SUPPORT)
      printf("CRT2 ");
    if (sd & ATOM_DEVICE_LCD2_SUPPORT)
      printf("LCD2 ");
    if (sd & ATOM_DEVICE_TV2_SUPPORT)
      printf("TV2 ");
    if (sd & ATOM_DEVICE_DFP2_SUPPORT)
      printf("DFP2 ");
    if (sd & ATOM_DEVICE_CV_SUPPORT)
      printf("CV ");
    if (sd & ATOM_DEVICE_DFP3_SUPPORT)
      printf("DFP3 ");
    if (sd & ATOM_DEVICE_DFP4_SUPPORT)
      printf("DFP4 ");
    if (sd & ATOM_DEVICE_DFP5_SUPPORT)
      printf("DFP5 ");
}

static void radeon_dump_bios_igp_slot_config(struct atom_context *ctx, uint16_t obj)
{
      uint16_t size, data_offset;
      uint8_t frev, crev;
      int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
      ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL;
      uint8_t obj_id, num, obj_type;

      obj_id = (obj & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
      num = (obj & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
      obj_type = (obj & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;

      if (obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR) {
          uint32_t slot_config, ct;

          atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);

          igp_obj = (ATOM_INTEGRATED_SYSTEM_INFO_V2 *)(ctx->bios + data_offset);

          if (igp_obj) {
            if (num == 1)
                slot_config = igp_obj->ulDDISlot1Config;
            else
                slot_config = igp_obj->ulDDISlot2Config;

            ct = (slot_config  >> 16) & 0xff;
            printf("\tConnector: %s\n", connector_names[ct]);
            printf("\tLane Config: 0x%04x\n", slot_config & 0xffff);
          }
      }
}

void radeon_dump_bios_object_table(struct atom_context *ctx)
{
      uint16_t size, data_offset;
      uint8_t frev, crev;
      int index = GetIndexIntoMasterTable(DATA, Object_Header);
      ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
      ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
      ATOM_ENCODER_OBJECT_TABLE *enc_obj;
      ATOM_OBJECT_TABLE *router_obj;
      ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL;
      ATOM_OBJECT_HEADER *obj_header;
      int i, j, k, path_size;

      atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);

      if (crev < 2)
            return;

      obj_header = (ATOM_OBJECT_HEADER *)(ctx->bios + data_offset);

      printf("\nSupported Devices: ");
      radeon_print_supported_devices(obj_header->usDeviceSupport);
      printf("\n");

      path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)(ctx->bios + data_offset + obj_header->usDisplayPathTableOffset);
      con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)(ctx->bios + data_offset + obj_header->usConnectorObjectTableOffset);
      enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)(ctx->bios + data_offset + obj_header->usEncoderObjectTableOffset);
      router_obj = (ATOM_OBJECT_TABLE *)(ctx->bios + data_offset + obj_header->usRouterObjectTableOffset);

      path_size = 0;
      for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
          uint8_t *addr = (uint8_t *)path_obj->asDispPath;
          ATOM_DISPLAY_OBJECT_PATH *path;
          addr += path_size;
          path = (ATOM_DISPLAY_OBJECT_PATH *)addr;

          if (obj_header->usDeviceSupport & path->usDeviceTag) {
            printf("\nDevice: ");
            radeon_print_supported_devices(path->usDeviceTag);
            printf("\n");
            // connector object
            printf("==== Connector Info ====\n");
            radeon_print_object(path->usConnObjectId);
            for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
                ATOM_COMMON_RECORD_HEADER *record;
                int record_base;
                uint16_t con_obj_id = le16_to_cpu(con_obj->asObjects[j].usObjectID);

                if (path->usConnObjectId == con_obj_id) {
                  record = (ATOM_COMMON_RECORD_HEADER *)
                      (ctx->bios + data_offset + le16_to_cpu(con_obj->asObjects[j].usRecordOffset));
                  record_base = le16_to_cpu(con_obj->asObjects[j].usRecordOffset);

                  while (record->ucRecordType > 0 &&
                         record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
                      //printf("record type %d\n", record->ucRecordType);

                      switch(record->ucRecordType) {
                      case ATOM_I2C_RECORD_TYPE:
                        {
                            ATOM_I2C_RECORD *i2c_record = (ATOM_I2C_RECORD *)record;
                            printf("  ATOM_I2C_RECORD_TYPE\n");
                            printf("    i2c mux:%d engine:%d hw_cap:%d\n",
                                 i2c_record->sucI2cId.bfI2C_LineMux,
                                 i2c_record->sucI2cId.bfHW_EngineID,
                                 i2c_record->sucI2cId.bfHW_Capable);
                            radeon_lookup_gpio(ctx, i2c_record->sucI2cId.bfI2C_LineMux);
                        }
                        break;
                      case ATOM_HPD_INT_RECORD_TYPE:
                        {
                            ATOM_HPD_INT_RECORD *hdp = (ATOM_HPD_INT_RECORD *)record;
                            printf("  ATOM_HPD_INT_RECORD_TYPE\n");
                            printf("    gpioid: %d, plugged pin state: 0x%x\n",
                                 hdp->ucHPDIntGPIOID, hdp->ucPluggged_PinState);
                        }
                        break;
                      case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
                        {
                            ATOM_CONNECTOR_DEVICE_TAG_RECORD *dev_tag_rec =
                              (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)record;
                            printf("  ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE\n");
                            printf("    Devices: ");
                            for (k = 0; k < dev_tag_rec->ucNumberOfDevice; k++) {
                              ATOM_CONNECTOR_DEVICE_TAG *dev_tag =
                                  &dev_tag_rec->asDeviceTag[k];
                              radeon_print_supported_devices(dev_tag->usDeviceID);
                            }
                            printk("\n");
                        }
                        break;
                      case ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE:
                        {
                            ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *cvtv =
                              (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *)record;
                            printf("  ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE\n");
                            printf("    gpioid: %d, tv active state: %d\n",
                                 cvtv->ucGPIOID, cvtv->ucTVActiveState);
                        }
                        break;
                      case ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE:
                        {
                            ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD *pcie =
                              (ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD *)record;
                            printf("  ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE\n");
                            printf("    %s\n", connector_names[pcie->ucSubConnectorType]);
                        }
                        break;
                      case ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE:
                        printf("  ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE\n");
                        break;
                      case ATOM_CONNECTOR_CF_RECORD_TYPE:
                        printf("  ATOM_CONNECTOR_CF_RECORD_TYPE\n");
                        break;

                      }
                      record = (ATOM_COMMON_RECORD_HEADER *)((char *)record + record->ucRecordSize);
                  }
                  break;
                }
            }
            radeon_dump_bios_igp_slot_config(ctx, path->usConnObjectId);
            printf("==== GPU Info ====\n");
            radeon_print_object(path->usGPUObjectId);
            printf("==== Encoder info ====\n");
            for (k = 0; k < ((path->usSize - 8) / 2); k++) {
                uint8_t obj_type = (path->usGraphicObjIds[k] & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;

                if (obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
                  radeon_print_object(path->usGraphicObjIds[k]);
                  for (j = 0; j < enc_obj->ucNumberOfObjects; j++) {
                      ATOM_COMMON_RECORD_HEADER *record;
                      int record_base;
                      uint16_t enc_obj_id = le16_to_cpu(enc_obj->asObjects[j].usObjectID);

                      if (path->usGraphicObjIds[k] == enc_obj_id) {
                        record = (ATOM_COMMON_RECORD_HEADER *)
                            (ctx->bios + data_offset + le16_to_cpu(enc_obj->asObjects[j].usRecordOffset));
                        record_base = le16_to_cpu(enc_obj->asObjects[j].usRecordOffset);

                        while (record->ucRecordType > 0 &&
                               record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
                            //printf("record type %d\n", record->ucRecordType);

                            switch(record->ucRecordType) {
                            case ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE:
                              printf("  ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE\n");
                              break;
                            case ATOM_ENCODER_DVO_CF_RECORD_TYPE:
                              printf("  ATOM_ENCODER_DVO_CF_RECORD_TYPE\n");
                              break;
                            case ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE:
                              printf("  ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE\n");
                              break;
                            }
                            record = (ATOM_COMMON_RECORD_HEADER *)((char *)record + record->ucRecordSize);
                        }
                        break;
                      }
                  }
                }
            }

            printf("==== Router Info ====\n");
            for (k = 0; k < ((path->usSize - 8) / 2); k++) {
                uint8_t obj_type = (path->usGraphicObjIds[k] & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;

                if (obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
                  radeon_print_object(path->usGraphicObjIds[k]);
                  for (j = 0; j < router_obj->ucNumberOfObjects; j++) {
                      ATOM_COMMON_RECORD_HEADER *record;
                      int record_base;
                      uint16_t router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);

                      if (path->usGraphicObjIds[k] == router_obj_id) {
                        record = (ATOM_COMMON_RECORD_HEADER *)
                            (ctx->bios + data_offset + le16_to_cpu(router_obj->asObjects[j].usRecordOffset));
                        record_base = le16_to_cpu(router_obj->asObjects[j].usRecordOffset);

                        while (record->ucRecordType > 0 &&
                               record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
                            //printf("record type %d\n", record->ucRecordType);

                            switch(record->ucRecordType) {
                            case ATOM_I2C_RECORD_TYPE:
                              {
                                  ATOM_I2C_RECORD *i2c_record = (ATOM_I2C_RECORD *)record;
                                  printf("  ATOM_I2C_RECORD_TYPE\n");
                                  printf("    i2c mux:%d engine:%d hw_cap:%d\n",
                                       i2c_record->sucI2cId.bfI2C_LineMux,
                                       i2c_record->sucI2cId.bfHW_EngineID,
                                       i2c_record->sucI2cId.bfHW_Capable);
                                  radeon_lookup_gpio(ctx, i2c_record->sucI2cId.bfI2C_LineMux);
                              }
                              break;
                            case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
                              {
                                  ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path =
                                    (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)record;
                                  printf("  ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE\n");
                                  printf("    mux type: %d, mux cntl pin: %d, mux state: %d\n",
                                       ddc_path->ucMuxType,
                                       ddc_path->ucMuxControlPin,
                                       ddc_path->ucMuxState[0]);
                              }
                              break;
                            case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
                              {
                                  ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *clk_data_path =
                                    (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)record;
                                  printf("  ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE\n");
                                  printf("    mux type: %d, mux cntl pin: %d, mux state: %d\n",
                                       clk_data_path->ucMuxType,
                                       clk_data_path->ucMuxControlPin,
                                       clk_data_path->ucMuxState[0]);
                              }
                              break;
                            case ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE:
                              printf("  ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE\n");
                              break;
                            }
                            record = (ATOM_COMMON_RECORD_HEADER *)((char *)record + record->ucRecordSize);
                        }
                        break;
                      }
                  }
                }
            }
          }
          path_size += path->usSize;
      }
}

void radeon_dump_bios_connector_table(struct atom_context *ctx)
{


}

void radeon_execute_aux_channel_table(struct atom_context *ctx)
{
      int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
      PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS params;

      memset(&params, 0, sizeof(params));

      params.lpAuxRequest = 0;
      params.lpDataOut = 0x100;
      params.ucChannelID = 0;
      
      atom_execute_table(ctx, index, (uint32_t *)&params);

}

void radeon_execute_hw_i2c_table(struct atom_context *ctx)
{
      int index = GetIndexIntoMasterTable(COMMAND, ReadEDIDFromHWAssistedI2C);
      READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION edid_data;
      int prescale;
      int i2c_clock = 50;
      int engine_clk = 0; //info->sclk * 100;

//    if (info->ChipFamily == CHIP_FAMILY_R520)
            prescale = (127 << 8) + (engine_clk * 10) / (4 * 127 * i2c_clock);
//    else if (info->ChipFamily < CHIP_FAMILY_R600)
            prescale = (((engine_clk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
//    else
//          prescale = (info->pll.reference_freq * 10) / i2c_clock;

      edid_data.usPrescale = prescale;
      edid_data.usVRAMAddress = 0;
      edid_data.ucSlaveAddr = 0xa0;
      //edid_data.ucLineNumber = radeon_output->ddc_i2c.hw_line;  

      atom_execute_table(ctx, index, (uint32_t *)&edid_data);


}



void dump_vram_table(struct atom_context *ctx)
{
      int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
      uint16_t data_offset;
      uint8_t crev, frev;
      uint16_t size;
      ATOM_VRAM_USAGE_BY_FIRMWARE *vram_usage;
      uint16_t fw_bytes;
      uint32_t start_offset;
      
      atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);

      vram_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
      start_offset = vram_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
      fw_bytes = vram_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
      printf("vram_usage 0x%08x %dkb\n", 
             vram_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
             vram_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);

      if (!fb_mem)
            printf("No card to dump VRAM from\n");
      else {
            void *backing;
            int fd;

            backing = kzalloc(fw_bytes, GFP_KERNEL);

            start_offset &= 0xfffffff;
            memcpy(backing, fb_mem + start_offset, fw_bytes);

            fd = open("/tmp/vram_usage", O_RDWR | O_CREAT, 0666);

            write(fd, backing, fw_bytes);

            close(fd);

            printf("EDID offsets crt1:0x%x lcd1:0x%x dfp1:0x%x crt2:0x%x df5:0x%x\n", ATOM_CRT1_EDID_ADDR,
                       ATOM_LCD1_EDID_ADDR, ATOM_DFP1_EDID_ADDR,
                       ATOM_CRT2_EDID_ADDR, ATOM_DFP5_EDID_ADDR);
                printf("DP train 0x%x\n", ATOM_DP_TRAINING_TBL_ADDR);

      }

}

static void cail_reg_write(struct card_info *card_info, uint32_t reg, uint32_t val)
{
      printf("reg write %d, %d\n", reg, val);
//    *(unsigned int * volatile)(ctrl_mem + reg) = val;  
}

static uint32_t cail_reg_read(struct card_info *card_info, uint32_t reg)
{
      printf("reg read %d\n", reg);
      return 0; //*(unsigned int * volatile)(ctrl_mem + reg);
}

static void fake_reg_write(struct card_info *card_info, uint32_t reg, uint32_t val)
{
      printf("reg write %d, %d\n", reg, val);
//    *(unsigned int * volatile)(ctrl_mem + reg) = val;  
}

static uint32_t fake_reg_read(struct card_info *card_info, uint32_t reg)
{
      printf("reg read %d\n", reg);
      return 0; //*(unsigned int * volatile)(ctrl_mem + reg);
}

struct atom_context *atom_init(void *bios)
{
  struct atom_context *ctx;

  memset(&my_card_info, 0, sizeof(struct card_info));

  if (ctrl_mem) {
        my_card_info.reg_read = cail_reg_read;
        my_card_info.reg_write = cail_reg_write;
  } else {
        my_card_info.reg_read = fake_reg_read;
        my_card_info.reg_write = fake_reg_write;
  }

  ctx = atom_parse(&my_card_info, bios);

  //atom_asic_init(ctx);
  return ctx;
}

void atom_dump(struct atom_context *ctx)
{

  radeon_dump_bios_connector_table(ctx);

  radeon_dump_bios_object_table(ctx);

  //dump_vram_table(ctx);

  //radeon_execute_aux_channel_table(ctx);

}

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